A memory device or memory can generally be described as hardware that can store data for later retrieval. Memory devices generally include a set of transistors used to store data (represented, for example, by an electrical charge) and a set of transistors used to control access to the data store. Individual transistors generally include a very thin insulating layer that separates a metal layer from a semiconductor layer. The insulator stops current flow when the transistor is switched “off”.
Ideally in the “off” scenario no current passes through the transistor and no power is consumed. The thickness of the insulator is small enough, however, that some current passes or “leaks” through the transistor even when turned “off”. The leakage current results in unnecessary power consumption. Although power consumption attributed to leakage current is small for an individual transistor, when multiplied over the millions of transistors that may be present in a memory device, the cumulative resultant power consumption attributed to leakage current is significant.
Memory storage densities continue to grow as consumers desire memory with larger capacity and smaller device sizes. Increasing memory storage density may be accomplished by reducing the size of the transistors in the memory device. Size reduction, or scaling, of the transistors is generally done in three dimensions, such that any reduction in the lateral dimensions is accompanied by a corresponding reduction in the vertical dimension. Generally, device operation in smaller transistors is similar to that of larger transistors only if scaling of both the lateral and vertical dimensions are substantially the same. The vertical size of such a transistor is, in part, determined by thickness of the insulating layer described earlier. Therefore, a reduction in the lateral size of the transistor demanded by a need for increasing storage densities leads to a reduction of insulating layer thickness.
Leakage current increases with decreasing thickness of the insulating layer. Therefore, a reduction in thickness of the transistor corresponds to larger leakage currents. For example, reduction of transistor sizes recently reached 65 nm and 45 nm, and will soon reach 32 nm. Leakage currents at the 65 nm node are generally less than 10 pA but at the 45 nm node leakage currents are greater than 20 pA. This increase in leakage current results in larger power consumption by the memory device.
One strategy to reduce power consumption is to prevent leakage current. Transistors used in memory cells require high performance and, as such, use low threshold voltage transistors. High threshold transistors, on the other hand, have significantly reduced leakage current when turned “off” but suffer from poor performance. Combining high threshold transistors with low threshold transistors can allow the high performance required of memory devices and low power consumption. Conventional memory designs place a high threshold transistor between the memory control circuitry and the negative supply voltage. This transistor is known as a periphery footswitch.
Use of high threshold transistors has, however, been limited to periphery control circuitry. As a result, only a fraction of the total leakage in the memory device is reduced. Transistors in other sections of the memory device continue to consume excess power through leakage current. Attempts at placing a footswitch in the core array have resulted in unacceptable ground bouncing or noise issues. Additionally, attempts at placing a high threshold transistor between the word line driver and the supply voltage has created abnormal behavior resulting from floating of the word line.
Another conventional method to reduce power consumption in the core array is the source biasing scheme. This scheme reduces leakage current but suffers from additional complexities. For example, layout complexity is significantly greater, which increases cost of design and manufacturing. Additionally, data retention is uncertain under source biasing schemes, and the power-on sequence for memory when coming out of sleep mode is very complex. Therefore, these schemes are difficult to implement in practical circuit design.
Thus, there is a need for a memory design with reduced power consumption.